module CPSFFT
#(
  parameter DATA_SIZE  = 32,
  parameter DFT_POINTS = 16
)(
  //OUTPUTS
  output [DATA_SIZE - 1:0] PRDATA,              //APB Read Bus
  output PREADY,                                //APB Ready Signal
  output PSLVERR,                               //APB Error Signal
  output INT_CPSFFT,                            //Interruption Signal
  //INPUTS
  input [DATA_SIZE - 1:0] PWDATA,               //APB Write Bus
  input [1:0] PADDR,                            //APB Address Bus
  input PSEL,                                   //APB Select Signal
  input PENABLE,                                //APB Enable Signal
  input PWRITE,                                 //APB Read/Write Signal
  input PCLK,                                   //APB Clock
  input PRESETn                                 //APB Reset 
);

  wire [DATA_SIZE - 1:0] bus_rd, bus_wr;
  wire [1:0] bus_addr;
  wire busy_n, write_en, read_en, bus_rdy;
  
  fft_core
  #(
    .DATA_SIZE  (DATA_SIZE  ),
    .DFT_POINTS (DFT_POINTS )
  )
    FFT_CORE
  (
    .bus_rd    ( bus_rd    ),
    .bus_rdy   ( bus_rdy   ),
    .interrupt ( INT_CPSFFT),
    .busy_n    ( busy_n    ),
    .bus_wr    ( bus_wr    ),
    .bus_addr  ( bus_addr  ),
    .read_en   ( read_en   ),
    .write_en  ( write_en  ),
    .enable    ( PENABLE   ),
    .clk       ( PCLK      ),
    .rst_n     ( PRESETn   )
  );
  
    apb_to_core
  #(
    .CORE_BUS_WIDTH ( DATA_SIZE ),
    .CORE_ADDR      ( 2 )
  )
   APB
  (
    .PRDATA        ( PRDATA   ),
    .PREADY        ( PREADY   ),      
    .PSLVERR       ( PSLVERR  ),     
    .core_bus_wr   ( bus_wr   ),  
    .core_write_en ( write_en ),
    .core_read_en  ( read_en  ),
    .core_addr     ( bus_addr ),  
    .PWDATA        ( PWDATA   ),     
    .PADDR         ( PADDR    ),      
    .PSEL          ( PSEL     ),       
    .PENABLE       ( PENABLE  ),    
    .PWRITE        ( PWRITE   ),     
    .PCLK          ( PCLK     ),       
    .PRESETn       ( PRESETn  ),    
    .core_bus_rd   ( bus_rd   ),
    .core_bus_rdy  ( bus_rdy  ),
    .core_busy_n   ( busy_n   ) 
  );
endmodule